[FPGA] Clock에 필요한 모듈 1) Prescaler Verilog Code

Block Diagram

Block Diagram

먼저, FPGA zybo 에서 제공하는 CLOCK (125Mhz) 을 usec, msec, sec 단위등으로 나눠, 단위별로 카운터하는데 필수가 되는 모듈입니다. 

 

1. Prescaler (clk / usec_clk / msec_clk / csec_clk / sec_clk )

module clock_usec(input clk, output reg clk_usec);

    reg [6:0] cnt_clk;
    
    always @(negedge clk) begin
        cnt_clk = cnt_clk + 1;
        if (cnt_clk > 124) cnt_clk = 0;
        if (cnt_clk > 63) clk_usec = 1;
        else clk_usec = 0;
    end
endmodule

module clock_msec(input clk_usec, output reg clk_msec);

    reg [9:0] cnt_usec;
    
    always @(negedge clk_usec) begin
        cnt_usec = cnt_usec + 1;
        if (cnt_usec > 999) cnt_usec = 0;
        if (cnt_usec > 499) clk_msec = 1;
        else clk_msec = 0;
    end

endmodule

module clock_csec(input clk_msec, output reg clk_csec);

    reg [6:0] cnt_msec;
    
    always @(negedge clk_msec) begin
        cnt_msec = cnt_msec + 1;
        if (cnt_msec > 9) cnt_msec = 0;
        if (cnt_msec > 4) clk_csec = 1;
        else clk_csec = 0;
    end

endmodule

module clock_sec_1(input clk_msec, output reg clk_sec_1);

    reg [9:0] cnt_msec;
    
    always @(negedge clk_msec) begin
        cnt_msec = cnt_msec + 1;
        if (cnt_msec > 999) cnt_msec = 0;
        if (cnt_msec > 499) clk_sec_1 = 1;
        else clk_sec_1 = 0;
    end

endmodule

module clock_sec_10(
    input inc_sec,
    input clk_sec_1, 
    output reg clk_sec_10,
    output reg [3:0] cnt_sec_1);

    wire inc_clk;
    
    xor(inc_clk, clk_sec_1, inc_sec); 
    
    always @(negedge inc_clk) begin
        cnt_sec_1 = cnt_sec_1 + 1;
        if (cnt_sec_1 > 9) cnt_sec_1 = 0;
        if (cnt_sec_1 > 4) clk_sec_10 = 1;
        else clk_sec_10 = 0;
    end    

endmodule

module clock_min_1(
    input clk_sec_10, 
    output reg clk_min_1,
    output reg [3:0] cnt_sec_10);

    
    
    always @(negedge clk_sec_10) begin
        cnt_sec_10 = cnt_sec_10 + 1;
        if (cnt_sec_10 > 5) cnt_sec_10 = 0;
        if (cnt_sec_10 > 2) clk_min_1 = 1;
        else clk_min_1 = 0;
    end

endmodule

module clock_min_10(
    input inc_min,
    input clk_min_1, 
    output reg clk_min_10,
    output reg [3:0] cnt_min_1 );

    wire inc_clk;
    
    xor(inc_clk, inc_min, clk_min_1);
    
    always @(negedge inc_clk) begin
        cnt_min_1 = cnt_min_1 + 1;
        if (cnt_min_1 > 9) cnt_min_1 = 0;
        if (cnt_min_1 > 4) clk_min_10 = 1;
        else clk_min_10 = 0;
    end

endmodule

 

2. FND Switcher 

2021.04.01 - [분류 전체보기] - [FPGA] Clock에 필요한 모듈 2) FND 4digit switcher Verilog Code

3. Decoder 7_seg

2021.04.01 - [분류 전체보기] - [FPGA] Clock에 필요한 모듈 3) Decoder for 7 Segments Verilog Code

4. UP/DOWN Counter 

2021.04.01 - [분류 전체보기] - [FPGA] Clock에 필요한 모듈 4) Up/Down Counter Verilog Code