[FPGA] - Stop Watch 구현하기 (Verilog C)

Stop Watch 도 Timer와 마찬가지로 다음의 구조로 이루어져 있습니다. 

up_down_controller를 어떻게 설계하느냐에 따라 Timer가 될수도있고 Stop Watch가 될 수 있습니다. 

 

Stopwatch_module 회로를 다음과 같이 설계하였습니다. 

버튼 1번 : Count Up

버튼 3번 : Reset

 

따라서 위 두개의 설계도를 기반으로 설계를 한 결과물 입니다.

 

아래는 StopWatch Module Verilog Code 부분입니다. 

module stop_watch_module(

    input clk,
    input [3:0] btn,
    output [3:0] com,
    output [6:0] seg_7
    );
    
    wire up_down = 0;
    wire [3:0] csec_1, csec_10, sec_1, sec_10;
    wire countup_enable;
    wire [3:0] debounced_btn;
    wire clk_usec, clk_msec, clk_csec;
    wire [3:0] hex_value;
    //wire countdown_enable_bar, clk_sec_1_bar, sec_down_clk;
    wire csec_up_clk, inc_clk, clk_csec_bar;
    wire sec_up_clk;
  //  wire led_off;
 //   wire btn3_bar;
   // wire time_out, end_of_count, toggle_enable;
        
    D_flip_flop DFF0 (.D(btn[0]), .clk(clk_msec), .reset(1'b1), 
        .preset(1'b1), .Q(debounced_btn[0]));
    D_flip_flop DFF1 (.D(btn[1]), .clk(clk_msec), .reset(1'b1), 
        .preset(1'b1), .Q(debounced_btn[1]));
    D_flip_flop DFF2 (.D(btn[2]), .clk(clk_msec), .reset(1'b1), 
        .preset(1'b1), .Q(debounced_btn[2]));
    D_flip_flop DFF3 (.D(btn[3]), .clk(clk_msec), .reset(1'b1), 
        .preset(1'b1), .Q(debounced_btn[3]));
    
    clock_usec G_usec (.clk(clk), .clk_usec(clk_usec));
    clock_msec G_msec (.clk_usec(clk_usec), .clk_msec(clk_msec));
    clock_csec G_csec (.clk_msec(clk_msec), .clk_csec(clk_csec));
    
    FND4digit_switcher S (
        .value_1(csec_1),
        .value_10(csec_10),
        .value_100(sec_1),
        .value_1000(sec_10),
        .clk_msec(clk_msec),
        .hex_value(hex_value),
        .com(com));
    decoder_7_seg D7 (.hex_value(hex_value), .seg_7(seg_7));
    
    not (clk_csec_bar, clk_csec);
    and (csec_up_clk, clk_csec_bar, countup_enable);
    
    not (btn2_bar, debounced_btn[2]);
    
    T_flip_flop T1 (
        .T(1'b1),
        .clk(debounced_btn[0]),
        .reset(btn2_bar),
        .Q(countup_enable)
    );
    
    counter_up_down_csec stopwatch_csec (
        .up_down(up_down),
        .up_down_clk(csec_up_clk),
        .reset(debounced_btn[2]),
        .count_1(csec_1),
        .count_10(csec_10),
        .inc_clk(inc_clk)
    );
    
    and (sec_up_clk, inc_clk, countup_enable);
    
    counter_up_down stopwatch_sec (
        .up_down(up_down),
        .up_down_clk(sec_up_clk),
        .reset(debounced_btn[2]),
        .count_100(sec_1),
        .count_1000(sec_10)
    );
    
//    always @(posedge debounced_btn[0]) begin
//        if (countup_enable) countup_enable <= 0;
//        else countup_enable <= 1;
//    end
    
endmodule