일 | 월 | 화 | 수 | 목 | 금 | 토 |
---|---|---|---|---|---|---|
1 | 2 | 3 | ||||
4 | 5 | 6 | 7 | 8 | 9 | 10 |
11 | 12 | 13 | 14 | 15 | 16 | 17 |
18 | 19 | 20 | 21 | 22 | 23 | 24 |
25 | 26 | 27 | 28 | 29 | 30 | 31 |
Tags
- out-of-order
- ABMA
- ERROR RESPONSE
- 구조적모델링
- APB3
- 스텝모터
- 레지스터슬라이스
- Verilog
- Low-power Interface
- T flip flop
- 카운터
- QoS
- AXI4
- FPGA
- AXI3
- Interoperability
- STM32
- atomic access
- stepmotor
- cacheable
- Multiple outstanding
- ordering model
- tff
- 펌웨어
- Multiple transaction
- single copy atomic size
- AMBA
- SoC
- 임베디드시스템
- FGPA #반도체설계 #verilog #시프트레지스터 #uart
Archives
- Today
- Total
CHIP KIDD
[FPGA] Timer Verilog Code 본문
카운트다운 모듈 동작 목표
1) 1번버튼을 누르면 초단위 UP
2) 2번버튼 누르면 min단위 UP
3) 3번버튼 누르면 Reset 초기화
4) 4번 버튼 누르면 Count Down 시작
+ 카운트 다운중에 0이 되면 자동으로 동작 멈추고 0으로 고정되며 불이켜짐
Dflipflop : 버튼의 채터링 방지
Tflipflop : T가 1일때, Clk에 어떤 값을 입력하면, 버튼 처럼 Toggle 되는 Output을 낼때 + 리셋값이 들어오면 출력값을 안내도록 할때
아래 코드를 보면 T1까지 기본 타이머 구현이고,
그 이후는 0값이 되면 카운트 다운이 자동으로 멈춰 0으로 초기화 하고, LED가 켜짐을 나타내는 코드
module cook_timer_module(
input clk,
input [3:0] btn,
output [3:0] led,
output [3:0] com,
output [6:0] seg_7
);
wire [3:0] sec_1, sec_10, min_1, min_10;
wire countdown_enable;
wire [3:0] debounced_btn;
wire clk_usec, clk_msec, clk_sec_1;
wire [3:0] hex_value;
wire countdown_enable_bar, clk_sec_1_bar, sec_up_clk;
wire sec_down_clk, sec_up_down_clk, dec_clk;
wire min_up_clk, min_down_clk, min_up_down_clk;
wire led_off;
wire btn3_bar;
wire time_out, end_of_count, toggle_enable;
D_flip_flop DFF0 (.D(btn[0]), .clk(clk_msec), .reset(1'b1),
.preset(1'b1), .Q(debounced_btn[0]));
D_flip_flop DFF1 (.D(btn[1]), .clk(clk_msec), .reset(1'b1),
.preset(1'b1), .Q(debounced_btn[1]));
D_flip_flop DFF2 (.D(btn[2]), .clk(clk_msec), .reset(1'b1),
.preset(1'b1), .Q(debounced_btn[2]));
D_flip_flop DFF3 (.D(btn[3]), .clk(clk_msec), .reset(1'b1),
.preset(1'b1), .Q(debounced_btn[3]));
clock_usec G_usec (.clk(clk), .clk_usec(clk_usec));
clock_msec G_msec (.clk_usec(clk_usec), .clk_msec(clk_msec));
clock_sec_1 G_sec_1 (.clk_msec(clk_msec), .clk_sec_1(clk_sec_1));
FND4digit_switcher S (
.value_1(sec_1),
.value_10(sec_10),
.value_100(min_1),
.value_1000(min_10),
.clk_msec(clk_msec),
.hex_value(hex_value),
.com(com));
decoder_7_seg D7 (.hex_value(hex_value), .seg_7(seg_7));
not (countdown_enable_bar, countdown_enable);
not (clk_sec_1_bar, clk_sec_1);
and (sec_up_clk, debounced_btn[0], countdown_enable_bar);
and (sec_down_clk, clk_sec_1_bar, countdown_enable);
or (sec_up_down_clk, sec_up_clk, sec_down_clk);
counter_up_down counter_sec (
.up_down(countdown_enable),
.up_down_clk(sec_up_down_clk),
.reset(debounced_btn[3]),
.count_1(sec_1),
.count_10(sec_10),
.dec_clk(dec_clk)
);
and (min_up_clk, debounced_btn[1], countdown_enable_bar);
and (min_down_clk, dec_clk, countdown_enable);
or (min_up_down_clk, min_up_clk, min_down_clk);
counter_up_down counter_min (
.up_down(countdown_enable),
.up_down_clk(min_up_down_clk),
.reset(debounced_btn[3]),
.count_1(min_1),
.count_10(min_10)
);
not(btn3_bar, debounced_btn[3]);
T_flip_flop T1 (
.T(1'b1),
.clk(toggle_enable),
.reset(btn3_bar),
.Q(countdown_enable)
);
nor (time_out,
sec_1[0], sec_1[1], sec_1[2], sec_1[3],
sec_10[0], sec_10[1], sec_10[2], sec_10[3],
min_1[0], min_1[1], min_1[2], min_1[3],
min_10[0], min_10[1], min_10[2], min_10[3]);
and (end_of_count, countdown_enable, time_out);
or (toggle_enable, debounced_btn[2], end_of_count);
nor (led_off,
debounced_btn[0], debounced_btn[1], debounced_btn[2], debounced_btn[3]);
T_flip_flop T2 (
.T(1'b1),
.clk(time_out),
.reset(led_off),
.Q(led[0])
);
endmodule
'반도체 > FPGA - Verilog' 카테고리의 다른 글
[FPGA] ADC ADC-Mux 설계 (Verilog Code) , 가변저항 10진수 출력 (0) | 2021.04.01 |
---|---|
[FPGA] ADC ADC-Mux 설계 (세팅) (0) | 2021.04.01 |
[FPGA] Clock에 필요한 모듈 4) Up/Down Counter Verilog Code (0) | 2021.04.01 |
[FPGA] Clock에 필요한 모듈 3) Decoder for 7 Segments Verilog Code (1) | 2021.04.01 |
[FPGA] Clock에 필요한 모듈 2) FND 4digit switcher Verilog Code (0) | 2021.04.01 |