[FPGA] ADC ADC-Mux 설계 (Verilog Code) , 가변저항 10진수 출력

이번장은 ADC모듈을 이용하여 , 6번 채널을 통해서 가변저항의 값을 10진수로 출력하겠습니다. 

 

 

module channel6_ADC(
    input clk,
    input vauxp6, vauxn6,
    output [3:0] com,
    output [6:0] seg_7
    
    );
     wire clk_usec, clk_msec;
     wire [3:0] hex_value;
     wire [4:0] channel_out;
     wire eoc_out;
     wire [15:0]do_out;
     wire [3:0] ones, tens, hundreds, thousands;
    
     
    clock_usec G_usec (.clk(clk), .clk_usec(clk_usec));
    clock_msec G_msec (.clk_usec(clk_usec), .clk_msec(clk_msec));
    
    FND4digit_switcher S (
        .value_1(ones),
        .value_10(tens),
        .value_100(hundreds),
        .value_1000(thousands),
        .clk_msec(clk_msec),
        .hex_value(hex_value),
        .com(com));
   
    decoder_7_seg D7 (.hex_value(hex_value), .seg_7(seg_7));
    
    XADC_test xadc(
        //.di_in(di_in),              // input wire [15 : 0] di_in
        .daddr_in({2'b00, channel_out}),        // input wire [6 : 0] daddr_in
        .den_in(eoc_out),            // input wire den_in
        //.dwe_in(dwe_in),            // input wire dwe_in
        //.drdy_out(drdy_out),        // output wire drdy_out
        .do_out(do_out),            // output wire [15 : 0] do_out //변환값
        .dclk_in(clk),          // input wire dclk_in
        .reset_in(1'b0),        // input wire reset_in
        //.vp_in(vp_in),              // input wire vp_in
        //.vn_in(vn_in),              // input wire vn_in
        .vauxp6(vauxp6),            // input wire vauxp6
        .vauxn6(vauxn6),            // input wire vauxn6
        .channel_out(channel_out),  // output wire [4 : 0] channel_out
        .eoc_out(eoc_out)          // output wire eoc_out
        //.alarm_out(alarm_out),      // output wire alarm_out
        //.eos_out(eos_out),          // output wire eos_out
        //.busy_out(busy_out)        // output wire busy_out
    );
    
//    always @(negedge clk_msec) begin
//        ones = do_out [3:0];
//        tens = do_out [7:4];
//        hundreds  = do_out [11:8];
//        thousands = do_out [15:12];
            
//    end
    
    BCD(
        .binary(do_out[15:8]), 
    .hundreds(hundreds),.tens(tens),.ones(ones)
    );
    
endmodule

 

module BCD(
    input [7:0] binary,
    output reg [3:0] hundreds,
    output reg [3:0] tens,
    output reg [3:0] ones
);

integer i;
    always @(binary) begin
        hundreds = 4'd0;
        tens = 4'd0;
        ones = 4'd0;
        for(i =7; i>=0; i = i-1) begin
            if(hundreds >=5)
                hundreds = hundreds + 3;
            if(hundreds >=5)
                tens = tens + 3;
            if(ones >=5)
             ones = ones + 3;
            
            hundreds = hundreds << 1;
            hundreds[0] = tens[3];
            tens = tens << 1;
            tens[0] = ones[3];
            ones = ones <<1;
            ones[0] = binary[i];
                    
      end 
    end

endmodule