[FPGA] Verilog Code - multiplexer/ demultiplexer

1. Multiplexer

module mutiplexer_8_1(
    input [7:0] D,
    input [2:0] S,
    output Y
    );
    
    wire Sbar0, Sbar1, Sbar2;
    wire [7:0] w;
    
    not (Sbar0, S[0]);
    not (Sbar1, S[1]);
    not (Sbar2, S[2]);
    and (w[0], D[0], Sbar2, Sbar1, Sbar0);
    and (w[1], D[1], Sbar2, Sbar1, S[0]);
    and (w[2], D[2], Sbar2, S[1], Sbar0);
    and (w[3], D[3], Sbar2, S[1], S[0]);
    and (w[4], D[4], S[2], Sbar1, Sbar0);
    and (w[5], D[5], S[2], Sbar1, S[0]);
    and (w[6], D[6], S[2], S[1], Sbar0);
    and (w[7], D[7], S[2], S[1], S[0]);
    or (Y, w[0], w[1], w[2], w[3], w[4], w[5], w[6], w[7]);

2. Demultiplexer

module demultiplexer_1_8(
    input D,
    input [2:0] S,
    output [7:0] Y
    );
    
    wire Sbar0, Sbar1, Sbar2;
  
    
    not (Sbar0, S[0]);
    not (Sbar1, S[1]);
    not (Sbar2, S[2]);
    and (Y[0], D, Sbar2, Sbar1, Sbar0);
    and (Y[1], D, Sbar2, Sbar1, S[0]);
    and (Y[2], D, Sbar2, S[1], Sbar0);
    and (Y[3], D, Sbar2, S[1], S[0]);
    and (Y[4], D, S[2], Sbar1, Sbar0);
    and (Y[5], D, S[2], Sbar1, S[0]);
    and (Y[6], D, S[2], S[1], Sbar0);
    and (Y[7], D, S[2], S[1], S[0]);
    
        
endmodule