[FPGA-Verilog : encoder / decoder/ 디코더를 이용한 7seg 출력]

디코더 / 인코더 

 

디코더

module decoder_3_8(
    input a, b, c, 
    output [7:0] decode
    );
    
    wire not_a, not_b, not_c;
    
    not (not_a, a);
    not (not_b, b);
    not (not_c, c); 
    and (decode[0], not_a, not_b, not_c);
    and (decode[1], not_a, not_b, c);
    and (decode[2], not_a, b, not_c);
    and (decode[3], not_a,b, c);
    and (decode[4], a, not_b, not_c);
    and (decode[5], a, not_b, c);
    and (decode[6], a, b, not_c);
    and (decode[7], a, b, c);
    
        
    
endmodule
module TB_decoder_3_8();
    
    reg a, b, c;
    wire [7:0] decode;

    decoder_3_8 G(.a(a),.b(b),.c(c),.decode(decode));

    initial begin 
    
        a = 0; b = 0; c = 0; #50;
        a = 0; b = 0; c = 1; #50;
        a = 0; b = 1; c = 0; #50;
        a = 0; b = 1; c = 1; #50;
        a = 1; b = 0; c = 0; #50;
        a = 1; b = 0; c = 1; #50;
        a = 1; b = 1; c = 0; #50;
        a = 1; b = 1; c = 1; #50;
    
    end

endmodule

인코더

module encoder_8_3(
    input [7:0] signal,
    output [2:0] code
    );
    
    or(code[0], signal[1],signal[3], signal[5], signal[7]);
    or(code[1], signal[2],signal[3], signal[6], signal[7]);
    or(code[2], signal[4],signal[5], signal[6], signal[7]);
    
endmodule

module TB_encoder_8_3();

    reg [7:0] signal; 
    wire [2:0] code;
    
    encoder_8_3 G (.signal(signal), .code(code));
    
    initial begin
        signal= 8'b00000001; #10;
        signal= 8'b00000010; #10;
        signal= 8'b00000100; #10;
        signal= 8'b00001000; #10;
        signal= 8'b00010000; #10;
        signal= 8'b00100000; #10;
        signal= 8'b01000000; #10;
        signal= 8'b10000000; #10;
        
    end

endmodule